1. Field of the Technology
The technology presented herein relates to a nonvolatile semiconductor memory device and more particularly, to a nonvolatile semiconductor memory device comprising a cross-point type memory cell array in which two-terminal structured memory cells each having a variable resistive element that can store data according to an electric resistance change by the application of an electric resistance are arranged in row and column directions, a plurality of word lines extending in a row direction and a plurality of bit lines extending in a column direction are provided, one ends of the memory cells in the same row are connected to the common word line, and the other ends of the memory cells in the same column are connected to the common bit line, and a writing method of data stored in the memory cell array.
2. Description of the Related Art
A flash memory is mainly used as the nonvolatile semiconductor memory device. Recently, problems in miniaturizing the flash memory includes a decrease in threshold voltage control due to lowering of a charge amount in a floating gate and a decrease in voltage resistance between a source and a drain due to reduction of a channel length, so that there is a limit of miniaturization of the flash memory in a plane direction.
Thus, the memory cell tends to be integrated from the plane to a laminated direction (vertical direction with respect to a substrate), and a new memory that can be laminated in the vertical direction is being developed. The new memory includes a FeRAM, a MRAM, a PRAM, a RRAM (Resistance Random Access Memory) and the like. Among these, the RRAM using a variable resistive element that can store data by electric resistance change by the application of an electric stress has been attracting attention because its memory cell can be integrated in the laminated direction.
As conventional techniques of the RRAM, there are known U.S. Patent Publication No. 6204139, W. W. Zhung et al., “Novell Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, IEDM, 2002, and I. G. Baek et al., “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses”, IEDM Technical Digest, pp. 587-590, December, 2004. A basic structure of the variable resistive element used in the RRAM includes a structure in which a transition metal oxide is sandwiched between an upper electrode and a lower electrode. The transition metal oxide includes PrxCa1-xMnO3, SmxCa1-xMnO3, TiO2, NiO, HfO2, ZrO2 and the like.
A memory cell array structure using the RRAM includes a cross-point type memory cell array (1R type array)(refer to N. Sakimura et al., “A 512 kb Cross-point Cell MRAM”, ISSCC, 16. Jan., 2003, for example). FIG. 1 is a perspective view showing the partial structure of a cross-point type memory cell array as one example, and FIG. 2 is a sectional view showing a memory cell in the memory cell array structure of the FIG. 1 in the vertical direction. In addition, electric insulators provided between the memory cells are not shown in the drawings.
According to the cross-point memory cell array, memory cells M are arranged at crossed points between a plurality of parallel bit lines BL and a plurality of parallel word lines WL that are orthogonal to the bit lines BL. The memory cell M comprises a variable resistive element 21. According to the cross-point memory cell array, since it is not necessary to form a switching element such as a transistor in each memory cell M, the memory cell array structure in which the plurality of memory cell arrays are laminated vertically can be easily provided. Thus, when the memory cells M are laminated by N layers, the area of the memory cell array can be 4F2/N (F: minimum processing line width and N: the number of layers). As a result, the nonvolatile memory device in which the area of the memory cell array is small can be implemented.
Here, the reading and writing operations of the cross-point memory cell array will be described. FIGS. 3 to 5 are schematic views showing the cross-point memory cell array structure. As shown in the drawings, a plurality of word lines WL0 to WLn extend in the vertical direction and a plurality of bit lines BL0 to BLn extend in the lateral direction. A memory cell is positioned at each cross-point between the word lines WL0 to WLn and the bit lines BL0 to BLn. In FIGS. 3 to 5, a variable resistive element at the cross-point between each word line and each bit line is not shown. In addition, to shift the resistance of the variable resistive element of the memory cell from low resistance to high resistance is defined as “program” while to shift the resistance of the variable resistive element of the memory cell from high resistance to low resistance is defined as “erase”. Thus, writing operation for the data of the memory cell includes a programming operation and an erasing operation.
First, a reading operation will be described. When information is read out from the memory cell selected as an object to be read out, as shown in FIG. 3, a readout voltage (+Vr) is applied to all the word lines, the readout voltage (+Vr) is applied to unselected bit lines that are not connected to the selected memory cell, and the selected bit line connected to the selected memory cell is set at 0V. Then, it is determined whether the variable resistive element of each memory cell on the selected bit line is in a high resistance state or a low resistance state by detecting whether a current flows in each word line or not.
Next, the programming operation will be described. When data is to be programmed in the memory cell selected as an object to be programmed, as shown in FIG. 4, a program voltage (+Vpp) is applied to the selected word line connected to the selected memory cell, a middle voltage (+Vpp/2) is applied to the unselected word lines that are not connected to the selected memory cell, and the middle voltage (+Vpp/2) is applied to the unselected bit lines that are not connected to the selected memory cell, and the selected bit line connected to the selected memory cell is set at the ground voltage (0V). Thus, the program voltage +Vpp is applied to the selected memory cell. Meanwhile, the middle voltage +Vpp/2 is applied to unselected memory cells A existing on the selected word line and unselected memory cells B existing on the selected bit line. In general, the program voltage Vpp is set so that data is not programmed in the memory cell at the middle voltage.
Next, the erasing operation will be described. When data is to be erased from the memory cell selected as an object to be erased, as shown in FIG. 5, an erase voltage (+Vpp) is applied to the selected bit line connected to the selected memory cell, the middle voltage (+Vpp/2) is applied to the unselected word lines that are not connected to the selected memory cell, the middle voltage (+Vpp/2) is applied to the unselected bit lines that are not connected to the selected memory cell, and the selected word line connected to the selected memory cell is set at the ground voltage (0V). Thus, the erase voltage −Vpp is applied to the selected memory cell. Meanwhile, the middle voltage −Vpp/2 is applied to the unselected memory cells A existing on the selected word line and the unselected memory cells B existing on the selected bit line. In general, the erase voltage Vpp is set so that data is not erased in the memory cell at the middle voltage having negative polarity.
In the programming and erasing operations, voltages applied to the selected word line, the unselected word line, the selected bit line and the unselected bit line are supplied from a word line decoder connected to each word line to perform a selecting or unselecting operation for the word line and a bit line decoder connected to each bit line to perform a selecting or unselecting operation for the bit line. In general, the word line and the word line decoder are electrically connected at the end of each word line, and similarly, the bit line and the bit line decoder are electrically connected at the end of each bit line. Therefore, at the time of programming operation, a program current flowing in the selected memory cell connected to the selected word line and the selected bit line is supplied from one of the word line decoder and the bit line decoder, to the other of the word line decoder and the bit line decoder through the selected word line, the selected bit line and the selected memory cell.
By the way, according to the cross-point memory cell array structure, when the word lines and the bit lines are arranged with minimum processing line widths and intervals, the memory cell area can be minimized. Meanwhile, the arrangement interval (distance between centers) of contact holes (through holes provided in an interlayer insulation film between two different wiring layers) used in electrically connecting each word line to the word line decoder and in electrically connecting each bit line to the bit line decoder is larger than the wiring interval (distance between center lines) of the word line and the bit line. This is because a contact pad of the wiring layer connected by the contact hole has to be larger than the diameter (minimum processing dimension) of the contact hole in order to ensure the alignment margin between the contact pad and the contact hole. Therefore, it is difficult to arrange the contact hole at the same wiring interval as that of the word line and the bit line arranged with the minimum processing line widths and intervals.
Since the interval of the contact hole is larger than the interval of the word line and the bit line, as shown in FIG. 6, when a contact C (a contact hole CH and a contact pad CP) to be arranged at the end of the word line to be electrically connected to the word line decoder is arranged each end so as to sandwich the memory cell array in such a manner that the contacts C are arranged at the right ends of the even-numbered word lines WL0, WL2, WL4, . . . and they are arranged at the left ends of the odd-numbered word lines WL1, WL3, WL5, . . . , the memory cell area of the cross-point memory cell array can be minimized and the contact can be effectively laid out.
Here, as shown in FIG. 6, when data is sequentially programmed in the memory cell array in which the contact is arranged at the end of the word line, each memory cell for programming is accessed in the order as shown in FIG. 7 in general before.
First, the word line WL0 designated by the lowest-order row address is selected and then the bit line BL0 designated by the lowest-order column address is selected to program data in the memory cell M00 connected to the word line WL0 and the bit line BL0. Continuously, while the same word line WL0 is selected, the column address is increased to select the bit lines BL1 to BLn sequentially to sequentially program data in memory cells M01, M02, . . . , M0n. After data have been programmed in all the memory cells connected to the word line WL0, the row address is increased by one to select the word line WL1 and the column address is returned to the lowest-order column address to select the bit line BL0 to program data in the memory cell M10 connected to the word line WL1 and the bit line BL0, and similarly while the same word line WL1 is selected, the column address is increased to sequentially select the bit lines BL1 to BLn to sequentially program data in memory cells M11, M12, . . . . M1n. After data has been programmed in all memory cells connected to the word line WL1, similarly, the row address is increased one by one to sequentially program data in memory cells connected to the word lines WL2 to WLn.
According to the case where data is sequentially written along the word lines, as for the even-numbered word lines WL0, WL2, WL4, . . . , data is sequentially written from the memory cell further from the contact C, that is, the memory cell further from the supply source of the word line voltage toward the contact, while as for the odd-numbered word lines WL1, WL3, WL5, . . . , data is sequentially programmed from the memory cell closer to the contact C, that is, the memory cell closer to the supply source of the word line voltage toward the side opposite to the contact.
FIG. 8 shows the relation between a programming time and a program current in the variable resistive element of a single memory cell. According to FIG. 8, it has been found that the programming time in the variable resistive element depends on the program current and it becomes considerably long as the program current is reduced.
The program current of the single memory cell is determined by a net program voltage applied to both ends of the single memory cell and the resistance value of the variable resistive element, so that the voltage (net program voltage) of the single memory cell is found by subtracting a voltage drop from a first connection point of the selected word line to the selected memory cell and a voltage drop from a second connection point of the selected bit line to the selected memory cell, from the program voltage applied between the first connection point between the selected word line and the word line decoder and the second connection point between the selected bit line and the bit line decoder. In addition, the voltage drop of the selected word line is determined by the wiring resistance of the selected word line, and a leak current flowing through the unselected memory cell positioned between the first connection point connected to the selected word line and the selected memory cell. Similarly, the voltage drop of the selected bit line is determined by the wiring resistance of the selected bit line, and a leak current flowing through the unselected memory cell positioned between the second connection point connected to the selected bit line and the selected memory cell.
FIG. 9 shows a case where the resistance values of the memory cells connected to the word line WL0 are all in a low resistance state RL, and programming is sequentially performed in the memory cells of that row so that the resistance value becomes high resistance state RH. When the programming is performed from the memory cell M00 at the left end that is furthest away from the contact to the right direction, since the resistance values of the other unselected memory cells M01 to M0n are all in the low resistance state RL before programming, at the time of programming in the memory cell M00, the leak current flowing in the selected word line is a maximum, and since the wiring resistance between the selected memory cell M0 and the contact is high, the voltage drop of the selected word line is a maximum, so that the net program voltage applied to the selected memory cell M00 is considerably lowered and the program current flowing in the selected memory cell M00 is reduced and its programming time is elongated. Meanwhile, at the time of programming of the memory cell M0n at the right end that is closest to the contact, since the resistance values of the other unselected memory cells M00 to M0n−1 are all in the high resistance state RH after programming, the leak current flowing in the word line is a minimum and since the wiring resistance between the selected memory cell M0n and the contact is low, the voltage drop of the selected word line is a minimum and the net program voltage applied to the selected memory cell M0n is not lowered so much, so that the program current flowing in the selected memory cell M0n is prevented from being reduced and the programming time is short. That is, when data is programmed from the memory cell furthest from the contact, the first memory cell is in the worst state in both leak current and wiring resistance, and the last memory cell is in the best state in both leak current and wiring resistance, so that there are large variations in the programming time.
Therefore, when a large amount of data is programmed, the total programming time is elongated because of the variations in the programming time. In addition, the variations in the programming time make it difficult to control the resistance value after the programming. Furthermore, when the program current is set based on the memory cell that is slow in the programming time, the program current is excessive for the memory cell that is fast in the programming time, which could reduce the reliability of the memory cell.